BI-651
64-bit RISC-V core with in-order dual issue pipeline based complex.
Balanced power efficiency and performance.
Key Features
- Configurable instruction set architecture:
- 64-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Atomic operation support (A extension)
- Compressed mode for better code density (C extension)
- IEEE 754-2008 compliant single precision floating point (F extension)
- IEEE 754-2008 compliant double precision floating point (D extension)
- Bit manipulation instructions support (B extension)
- Scalar cryptography instructions support (K extension)
- Digital signal processing instructions support (P extension)
- Decode: up to 2 instructions at cycle
- Execute: up to 2 instructions at cycle
- Up to 4 cores in complex
- Machine, Supervisor and User modes
- 9 stage in-order pipeline
- Advanced branch predictor: BTB, BHT, RAS
- Sv39 Virtual Memory support
- 4 to 32 KiB, 2 to 8-way L1 I-cache
- 4 to 32 KiB, 2 to 8-way L1 D-cache
- Integrated 128 KiB to 2 MiB L2 Cache
- L2 stride prefetcher
- Interrupts
- Platform Level Interrupt Controller (PLIC)
- Multi-Core Local Interruptor (CLINT): timer + software interrupts
- Local interrupt support to provide fast handling
- Core Local Interrupt Controller (CLIC)
- Non-Maskable Interrupts (NMIs)
- ECC memory protection (SEC-DED)
- Enhanced physical memory protection (Smepmp support)
- Integrated debug controller including HW breakpoints
- System bus access
- Compact JTAG support
- Trace support
- Power management support
- AXI system interface
- AXI peripheral interface
- AXI front-port interface for accelerator coherent access
- Performance
- 2.75 DMIPS/MHz
- 4.64 CoreMark/MHz
- 3.34 SPEC2006 INT/GHz
- Frequency (full place and route)
- 1 GHz (TSMC, 28nm HPC+, 7-track, SSG corner)
- 1.4 GHz (TSMC, 12nm, 9-track, SSG corner)
- 2.1 GHz (TSMC, 12nm, 9-track, TT corner)
SMP support
BI-651 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Memory coherency between cores allows to use core complex in SMP mode and run common operation system on all cores.
Coherency with periphrals and accelerators
Core complex has special AXI front port connected to coherency controller which provides coherent access for periphrals and accelerators to cached memory ranges simplifies software development and improves performance.
Memory subsystem
Fully non-blocking L1/L2 caches with out-of-order requests processing. Multiple "on-the-fly" requests in L1/L2 caches. L2 cache prefetcher with stride detection of stream and with configurable number of streams. Parallel hardware page table walk for several TLB misses. L1 and L2 TLBs.
Power management
Several power saving modes:
- After WFI instruction core stops its clock (WFI state)
- WFI state + core memories in retention state
- WFI state + core memories in shutdown state
- Core is power-off
- L2 cache memories are shutdown (with ¼ granularity)
- Core complex is power-off
Safe enter/exit from/to these modes:
- Cache flushes to prevent data loss
- "Wave"-based memories on/off
Test platform and software package
FPGA testbed for BI series includes complete set of tools to run OS Linux and communicate with it using Ethernet. All necessary software including Linux build, drivers and manuals are provided.
Development Tools
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
3rd Party Development Tools
IAR Embedded Workbench® offers excellent optimization technology to ensure developers that the application fits the required needs and optimizes the utilization of on-board memory and necessary speed. In this first release code density is already small comparing to other available tools. However, more optimizations are expected in future releases to generate even smaller code.
SEGGER Embedded Studio for RISC-V is the development environment for devices based on the open RISC-V architecture. Embedded Studio offers a complete solution to develop and debug your application. It enables you to use the complete development solution, including toolchain, optimized run-time library, core simulator and hardware debugging with the J-Link debug probes.
TRACE32® debugger for RISC-V. Lauterbach is the world's largest producer of complete, modular and upgradeable microprocessor development tools worldwide with experience in making world class debuggers and real-time trace since 1979.
Compatible Debug Probes
BI-651 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
