RISC-V Summit China in Hangzhou was one of the three largest RISC-V professional events in the world and the largest annual RISC-V event in China. More than 3,000 professionals from 100+ companies, research institutes and open source communities attended, with more than 500,000 viewers watching the online broadcast.

At its booth, CloudBEAR presented its updated line of processor cores. In addition, senior engineer Dmitry Zakharov made a report on the application of P-expansion for RISC-V instruction set architecture (ISA) in digital signal processing algorithms. P-extension can be used to optimize digital signal processing algorithms on embedded devices and small cores, providing high performance in data processing. The example of a compact library of DSP primitives developed by CloudBEAR, compatible with the CMSIS-DSP interface, showed how P-extension is used to optimize functions, opening up new possibilities for voice processing and speech recognition in applications.

Participating in RISC-V Summit China was an important step for our company in strengthening our market position and expanding our partner network.

RISC-V's open instruction set architecture (ISA) standard, based on the principles of reduced instruction set computers (RISC), is becoming increasingly popular in applications ranging from embedded systems to high-performance computing due to its open and free features.