RISC-V Meetup 2024

On April 15, 2024, a small but significant event took place in St. Petersburg - the first technical meetup of the Russian RISC-V Alliance. At it, CloudBEAR's Senior Software Engineer Dmitry Zakharov spoke about the application of the P-extension to the RISC-V instruction set architecture (ISA) for digital signal processing algorithms.

The P-extension is an instruction set for accelerating integer and fixed-point arithmetic and includes about 330 instructions in the current version. This extension works with general-purpose registers (GPRs) and can be thought of as operating on small vectors of data, with the interpretation of the vector being determined by the instruction code. The P-extension is also used to accelerate digital signal processing algorithms on embedded devices and small cores.

Its development began in 2016 with the goal of creating a more compact alternative to vector extensions for integer arithmetic in RISC-V ISA. In 2017, Andes proposed its work on P-extension as the basis for the standard, and development of the specification has been ongoing since then. The current version of the P-extension specification is 0.9.1, and work is currently underway, led by SoftFloat project author John Hauser, to validate the core instruction set and defer the rest for the future.

The P-extension can be used in a variety of applications, including voice processing on endpoint devices, speech recognition, and running machine learning algorithms on microcontrollers. And while its specification has yet to be ratified, there are already a number of chips, mostly based on Andes cores, that support it.

The CloudBEAR team developed a compact library of DSP primitives for microcontrollers and devices compatible with the CMSIS-DSP interface, and optimized a limited set of features for the first version using P-extension.