BR-350

32-bit RISC-V embedded core with in-order single issue pipeline.
Optimized for low power and small area. Perfectly fits for embedded control.

Request Info

Key Features

Configurable instruction set architecture:

32-bit RISC-V with 32 integer registers (I extension)
Integer multiplication and division (M extension)
Atomic operation support (A extension)
Compressed mode for better code density (C extension)
IEEE 754-2008 compliant single precision floating point (F extension)
IEEE 754-2008 compliant double precision floating point (D extension)
User mode interrupt handlers (N extension)
Bit manipulation instructions support (B extension)
Scalar cryptography instructions support (K extension)
Digital signal processing instructions support (P extension)

Single instruction issue
Machine and User modes
8 stage in-order pipeline
Advanced branch predictor: BTB, BHT, RAS
Configurable memory subsystem: L1 I/D-caches, TCMs
Front-port to access TCMs by external masters
Configurable interrupt subsystem

Platform Level Interrupt Controller (PLIC)
Core Local Interruptor (CLINT): timer + software interrupts
Local interrupt support to provide fast handling
Core Local Interrupt Controller (CLIC)
Non-Maskable Interrupts (NMIs)

ECC memory protection (SEC-DED)
Physical memory protection
Integrated debug controller including HW breakpoints
System bus access
Compact JTAG support
Trace support
Power management support
AXI/AHB configurable interfaces
Performance

1.7 DMIPS/MHz
3.29 CoreMark/MHz

Frequency (full place and route)

1 GHz (TSMC, 28nm HPC+, 7-track, SSG corner)

Memory subsystem

Support of configurable TCMs address ranges. TCM arbiter allows TCMs be accessible by fetch, load/store and via front-port. Optional instruction/data caches may be used with the following features:

N-way set associative
Configurable cache line
Prefetcher
Priority chunk support

Power management

Core completes all activity including cache requests and enter WFI mode. Support of external power management unit to provide clock gating and memory sleep.

Security

Physical memory protection (PMP) is key mechanism to provide isolation between different software components and limit their access to hardware. Up to 16 PMP regions are supported in BR-350.

Multi-core support

Preintegrated and tested subsystem is available. Flexible bus infrastructure to connect the cores itself and external world is supported. Different inter core communication mechanisms are possible:

Software interrupts in CLINT
Atomic in neighbor core TCMs

Development Tools

Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.

3rd Party Development Tools

IAR Embedded Workbench® offers excellent optimization technology to ensure developers that the application fits the required needs and optimizes the utilization of on-board memory and necessary speed. In this first release code density is already small comparing to other available tools. However, more optimizations are expected in future releases to generate even smaller code.

SEGGER Embedded Studio for RISC-V is the development environment for devices based on the open RISC-V architecture. Embedded Studio offers a complete solution to develop and debug your application. It enables you to use the complete development solution, including toolchain, optimized run-time library, core simulator and hardware debugging with the J-Link debug probes.

TRACE32® debugger for RISC-V. Lauterbach is the world's largest producer of complete, modular and upgradeable microprocessor development tools worldwide with experience in making world class debuggers and real-time trace since 1979.

Compatible Debug Probes

BR-350 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified: