System controller for power management and secure boot. Fully addressable memory space. Perfectly fit to organize crypto subsystem using 64-bit B extension.
Support of configurable TCMs address ranges. TCM arbiter allows TCMs be accessible by fetch, load/store and via front-port. Optional instruction cache may be used with the following features:
Core finalizes all activity including I-cache requests and enter to WFI mode. Support of external power management unit to provide clock gating and memory sleep.
Physical memory protection (PMP) is key mechanism to provide isolation between different software components and limit their access to hardware. Up to 16 PMP regions are supported in BM-610.
Preintegrated and tested subsystem is available. Flexible bus infrastructure to connect the cores itself and external world is supported. Different inter core communication mechanisms are possible:
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
TRACE32® debugger for RISC-V. Lauterbach is the world's largest producer of complete, modular and upgradeable microprocessor development tools worldwide with experience in making world class debuggers and real-time trace since 1979.
BM-610 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
Most of known real time operation systems (FreeRTOS, Apache Mynewt, Zephyr Project) have RISC-V port. You are ready to develop your application for BM-610 using them right away after download it.