Key Features
- Architecture: RV64IMCAFNB
- 64-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Compressed mode for better code density (C extension)
- Atomic operation support (A extension)
- IEEE 754-2008 compliant single precision floating point (F extension)
- User-level interrupt support (N extension)
- Bit manipulation instructions support (B extension)
- Machine and User modes
- 2-3-stage pipeline
- Configurable branch predictor
- Static: may be used to optimize area
- Dynamic (micro-BTB): may be used to optimize performance
- Optional instruction cache to accelerate access to slow memory
- Configurable interrupt subsystem
- Platform Level Interrupt Controller (PLIC)
- Core Local Interruptor (CLINT): timer + software
- Local interrupt support to provide fast handling
- Core Local Interrupt Controller (CLIC)
- Physical memory protection
- Integrated debug controller including HW breakpoints
- Trace support
- Power management support
- Configurable external interface: AHB-lite, AXI4
- Performance
- 1.89 DMIPS/MHz
- 3.84 CoreMark/MHz
- Frequency: up to 700 MHz (TSMC, 28nm HPC+, 9t, SVT, SSG corner)
64-bit housekeeper core
System controller for power management and secure boot. Fully addressable memory space. Perfectly fit to organize crypto subsystem using 64-bit B extension.
Memory subsystem
Support of configurable TCMs address ranges. TCM arbiter allows TCMs be accesible by fetch, load/store and via front-port. Optional instruction cache may be used with the following features:
- N-way set associative
- Configurable cache line
- Prefetcher
- Priority chunk support
Power management
Core finalizes all activity including I-cache requests and enter to WFI mode. Support of external power management unit to provide clock gating and memory sleep.
Security
Physical memory protection (PMP) is key mechanism to provide isolation between different software components and limit their access to hardware. Up to 16 PMP regions are supported in BM-610.
Multi-core support
Preintegrated and tested subsystem is available. Flexible bus infrastructure to connect the cores itself and external world is supported. Different inter core communication mechanisms are possible:
- Software interrupts in CLINT
- Atomic in neighbor core TCMs
Development Tools
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
3rd Party Development Tools
IAR Embedded Workbench® offers excellent optimization technology to ensure developers that the application fits the required needs and optimizes the utilization of on-board memory and necessary speed. In this first release code density is already small comparing to other available tools. However, more optimizations are expected in future releases to generate even smaller code.
SEGGER Embedded Studio for RISC-V is the development environment for devices based on the open RISC-V architecture. Embedded Studio offers a complete solution to develop and debug your application. It enables you to use the complete development solution, including toolchain, optimized run-time library, core simulator and hardware debugging with the J-Link debug probes.
TRACE32® debugger for RISC-V. Lauterbach is the world's largest producer of complete, modular and upgradeable microprocessor development tools worldwide with experience in making world class debuggers and real-time trace since 1979.
Compatible Debug Probes
BM-610 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
Powerful Software Ecosystem
Most of known real time operation systems (FreeRTOS, Apache Mynewt, Zephyr Project) have RISC-V port. You are ready to develop your application for BM-610 using them right away after download it.
