BI-652
64-bit RISC-V core with in-order dual issue pipeline based complex.
Balanced power efficiency and performance.
64-bit RISC-V core with in-order dual issue pipeline based complex.
Balanced power efficiency and performance.
BI-652 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Additional coherency controller provides coherent access for accelerators via AXI front port to cached memory ranges simplifies software development and improves performance.
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
IAR Embedded Workbench® offers excellent optimization technology to ensure developers that the application fits the required needs and optimizes the utilization of on-board memory and necessary speed. In this first release code density is already small comparing to other available tools. However, more optimizations are expected in future releases to generate even smaller code.
SEGGER Embedded Studio for RISC-V is the development environment for devices based on the open RISC-V architecture. Embedded Studio offers a complete solution to develop and debug your application. It enables you to use the complete development solution, including toolchain, optimized run-time library, core simulator and hardware debugging with the J-Link debug probes.
TRACE32® debugger for RISC-V. Lauterbach is the world's largest producer of complete, modular and upgradeable microprocessor development tools worldwide with experience in making world class debuggers and real-time trace since 1979.
BI-652 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified: