Configurable and extensible 32/64-bit RISC-V core. Selectable set of standard and custom extensions.

  • 32/64-bit RISC-V with 32 interger registers (I extension)
  • Integer multiplication and division (M extension)
  • Atomic operation support (A extension)
  • Compressed mode for better code density (C extension)
  • IEEE 754-2008 compliant single and double precision floating point (F, D extensions)
  • Custom ISA extensions

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Configurable memory subsystem. Caches, Tightly coupled memories.

Configurable instruction and data caches. Selectable cache size, line width, request buffers size. Data caches implements write back strategy for memory traffic reduction. Optionally tightly coupled memories are supported for application requires low-latency and deterministic response.

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Software tools. Compiler, debug, IDE.

Complete set of RISC-V tools for software development. Development and debug tools include OpenOCD, GDB, and Eclipse IDE.

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