High performance multi-core platform IP. Based on RISC-V cores.

Linux capable multi-core platform based on high-performance 32/64-bit RISC-V ISA compliant cores with shared L2 cache.

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Customizable ISA for certain workloads. Networking, SSD, baseband control, and MAC layer applications.

Improve performance of customer's target applications by adding processor instructions.

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Full coherency support. Standard SoC interfaces AXI/ACE buses.

Standard system-on-chip bus interfaces including cache coherency protocols support.

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